Using Rotator Transformations to Simplify FFT Hardware Architectures

Scalable FFT Architecture vs. Multiple Pipeline FFT Architectures Hardware Implementation and Cost

— This paper presents a family of architectures for FFT implementation based on the decomposition of the perfect shuffle permutation, which can be designed with variable number of processing elements. This provides designers with a trade-off choice of speed vs. complexity (cost and area.). Hardware comparison to other existing pipeline architecture presented based on implementation of 1024-poin...

FFT Compiler: From Math to Efficient Hardware

This paper presents a high-level compiler that generates hardware implementations of the discrete Fourier transform (DFT) from mathematical specifications. The matrix formula input language captures not only the DFT calculation but also the implementation options at the algorithmic and architectural levels. By selecting the appropriate formula, the resulting hardware implementations (described ...

Optimisation of Hardware Compilation using Programmable Transformations

Using XML Transformations for Enterprise Architectures

In this paper we report on the use of XML transformations in the context of Enterprise Architectures. We show that XML transformation techniques are valuable to the analysis, selection and, especially, the visualization of enterprise architectures. We propose a way to describe architectural information within a single XML document. Moreover, we propose transformational techniques to extract vie...

Universally Composable Firewall Architectures Using Trusted Hardware

Network firewalls are a standard security measure in computer networks that connect to the Internet. Often, ready-to-use firewall appliances are trusted to protect the network from malicious Internet traffic. However, because of their black-box nature, no one can be sure of their exact functionality. We address the possibility of actively compromised firewalls. That is, we consider the possibil...